Semiconductor component

ABSTRACT

The invention is directed to a semiconductor component having a semiconductor body with two principal faces, at least two electrodes at least one electrode being provided on a principal face, and zones of a conductivity type opposite one another that are arranged in alternation in the semiconductor body and extend perpendicularly to the two principal faces. For an application of a voltage to the two electrodes, the zones arranged in alternation mutually clear of charge carriers so that an essentially constant field strength is built up in the semiconductor body between the two electrodes These zones arranged in alternation inventively contain at least one cavity that is preferably closed by a glass layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention is directed to a semiconductor component with asemiconductor body having two principal faces, at least two electrodes,at least one electrode being provided on a principal face. The componenthas zones of mutually opposite conductivity type that are arranged inalternation in the semiconductor body and extend perpendicularly to thetwo principal faces. When voltage is applied to the two electrodes, thezones arranged in alternation are mutually cleared of charge carriers,so that an essentially constant field strength is built up in thesemiconductor body between the two electrodes.

2. Description of the Related Art

German patent DE 43 09 764 discloses a similar semiconductor component.This publication, discloses a power MOSFET with a semiconductor bodyhaving an inner zone of the first conductivity type, having a base zoneof the second conductivity type that adjoins the inner zone and a firstprincipal face of the semiconductor body and into which a source zone isembedded, and having a drain zone adjoining one of the principal facesof the semiconductor body. Additional zones of the second conductivitytype and further additional zones of the first conductivity type thatlie between the additional zones of the second conductivity type andthat are more highly doped than the inner zone are provided in the innerzone.

As a result of the “junction-trench” principle realized in this powerMOSFET, the name of this principle being based on the generation of theadditional zones by trenches, the specific turn-on resistance of highlyinhibiting DMOS transistors can be substantially improved: the driftzone that is otherwise uniformly doped in DMOS transistors, is replacedby the alternately arranged zones of mutually opposite conductivitytype, i.e., by n-doped zones and p-doped zones arranged in alternation.These n-doped zones and p-doped zones already mutually clear theircharge carriers for small voltages applied to the respective electrodes,so that, similar to a PIN diode, a nearly constant field strengthbetween the two electrodes, i.e., the drain electrode or, respectively,the highly doped n⁺ drain terminal and the source electrode or,respectively, the p-conductive semiconductor body can build up in such aDMOS transistor when an inhibit voltage is applied. The n-doped zonescan thereby be more highly doped by about one order of magnitude, whichleads to a corresponding reduction of the turn-on resistance.

The above-described principle of clearing the drift region of chargecarriers is also applied in lateral resurf (reduced surface fieldtransistors), as described in an article “1200 V High-Side LateralMOSFET in Junction-Isolated Power IC Technology Using TwoField-Reduction Layers”, by J. S. Ajit, Dan Kinzer and Niraj Ranjan in“International Rectifier”, 233 Kansas Street, El Segundo, Calif. 90245,pages 230-235. Such lateral resurf transistors can be more simplymanufactured than vertical structures with zones of differentconductivity type in alternation. The lateral format, however, causes asubstantially greater area requirement that is greater by a factor ofapproximately 10 than that given vertical structures.

Various paths are currently taken for manufacturing zones ofalternatingly changing conductivity type extending vertically to theprincipal faces of a semiconductor body, i.e., n-doped zones and p-dopedzones: in a first method, build-up technique is employed in which then-doped zones and the p-doped zones are “built up” step-by-step with theassistance of corresponding masks. A second method that is currentlyunder much discussion comprises etching deep trenches or, respectively,holes in, for example, an n-doped semiconductor body and epitaxiallyfilling the holes that have thus arisen with oppositely dopedsemiconductor material, preferably silicon. For voltages on the order ofmagnitude of 600 V, the trenches or, respectively, holes must beintroduced approximately 40 μm deep and should comprise a depth thatdoes not significantly fall below 2 μm.

This second method allows significantly smaller grids and, thus, smallerturn-on resistances to be realized than with the build-up technique. Thefilling of the trenches or, respectively, holes, however, presents agreat unanswered problem whether or not it will ever be possible to fillthe trenches bubble-free. In order to achieve the desired dielectricstrength for voltage on the order of magnitude of 600 V, the trenchesor, respectively, holes should have a depth of 40 μm. The manufacture ofa vertical resurf transistor with the methods being currently developedposes problem when a dielectric strength up to approximately 600 V ormore is to be achieved.

German patent DE 19 600 400 A1 discloses a micro-mechanical componentwith a planarized cover on a cavity. This cover comprises a membranelayer and a cover layer that is preferably composed of doped glass. Thecover layer is subjected to a flow step, in which this layer does notflow into the cavity but rather forms a planar cover at an upper orlower edge.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductorcomponent of the species initially cited such that the component can beproduced without the problems such as bubbles in trenches, discussedabove. An additional object a method for manufacturing such asemiconductor component as well as the advantageous employment of it.

This object is achieved by semiconductor component is providedcomprising a semiconductor body with two principal faces, at least twoelectrodes wherein at least one of the electrodes is provided on one ofthe principal faces, and zones of a conductivity type opposite oneanother that are arranged in alternation in the semiconductor body andextend perpendicularly to the two principal faces, an application of avoltage to the two electrodes mutually clearing the zones of chargecarriers so that an essentially constant field strength is built up inthe semiconductor body between the two electrodes the containing atleast one cavity that is closed by a glass layer or by a sputteredlayer.

This object is also achieved by a method for manufacturing asemiconductor component, comprising the sequential steps of introducingtrenches into a semiconductor body; applying a thin epitaxial layer or adoped oxide layer on the inside walls of the trenches, producing aremaining cavity, and closing the remaining cavity of the trenches witha doped glass layer or a sputtered layer.

Advantageous developments of the invention are recited below.

What is critical about the inventive semiconductor component is that itcontains at least one cavity that can have a trench structure with awidth of, for example, 1 μm and a depth of, for example, 40 μm. Thiscavity is closed at its end lying opposite the one principal face, towhich end a glass layer can be utilized. This glass layer can, forexample, be composed of doped borophosphorous silicate (BPSG). Anotherpossibility for closing the cavity is comprised in sputtering a coverlayer.

The inside walls of the cavity can be provided with a passivation layerof, for example, silicon dioxide.

What is critical about the inventive semiconductor component is that thecomplete filling of holes or, respectively, trenches is foregone. On thecontrary, the trenches remain after the manufacture of the oppositelydoped zones arranged in alternation. This zones can be generated, forexample, by etching trenches and subsequent epitaxial deposition or bedeposition of a doped oxide onto the inside surface of the trenches andsubsequent drive-out from the doped oxide.

The standard etching technique can be utilized for the production of thetrenches themselves or, on the other hand, an electrochemical method canbe utilized. It is significant, however, that the trenches still have anopening of approximately 1 μm over their entire depth of, for example,40 μm after the production of the zones that are doped opposite oneanother.

The inside wall of the trenches is passivated by a thin oxide layerbefore closing these trenches, a gate oxide layer that, for example, is50 nm thick may be utilized for this purpose.

The closing of the trenches or, respectively, holes can, for example, beundertaken by deposition of a doped glass such as, for example,borophosphorous silicate glass and subsequent flowing in a vacuum.However, a closure layer can also be applied onto the openings of thetrenches or, respectively, holes by sputtering.

After application of the doped glass, this closure layer iswet-chemically etched back in a standard way in diluted hydrofluoricacid (HF), so that a planar surface structure arises.

When a vertical resurf transistor is manufactured, then the transistorstructure can be subsequently built up between the trenches with astandard DMOS cell. However, it is also possible, for example, toproduce a DMOS transistor first and to subsequently etch the trenchesor, respectively, holes and to then—explained above, dope and closethese.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in greater detail below on the basis of thedrawings.

FIG. 1 is a cross-section through a semiconductor arrangement forexplaining a first method for generating trenches and layers that areoppositely doped in alternation;

FIG. 2 is a cross-section through a semiconductor arrangement forexplaining a second method for generating trenches and layers that areoppositely doped in alternation;

FIGS. 3-5 are cross-sections for explaining a method for closing thetrenches;

FIG. 6 is a cross-section through a DMOS transistor according to anexemplary embodiment of the invention; and

FIG. 7 is a cross-section through a DMOS transistor according to anotherexemplary embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a semiconductor body 1 composed of an n⁺-conductive region2 and a p-conductive region 3. The p-conductive region 3 can, forexample, be formed by epitaxial deposition on the n⁺-conductive region2, which serves as a substrate.

Trenches 4 having a depth T of approximately 40 μm and a width B ofapproximately 3 μm are introduced into the p-conductive region 3 byetching. An electrochemical method can also be utilized instead ofetching. The etching depth can also be less than the thickness of theregion 3.

An n-conductive epitaxial layer 5 is then deposited in the trenches 4,which has a layer thickness d of approximately 1 μm. After applicationof this epitaxial layer 5, a cavity 6 that still has a width b ofapproximately 1 μm thus remains in the trench 4.

The respective epitaxial layers 5 and the p-conductive region 3 thusform zones of mutually opposite conductivity type that are arranged inalternation and extend perpendicular to the two principal faces of thesemiconductor body 1.

FIG. 2 illustrates another method for manufacturing this zones ofmutually opposite conductivity type: in this method, too, trenches 4having a width of approximately 2.2 through 3 μm are introduced into thep-conductive region 3 down to the n⁺-conductive region 2. Instead of theepitaxial layer 5, however, a doped oxide layer 8, for example, a dopedsilicon dioxide layer, is deposited onto the inside surface of thetrenches 4, this layer 8 being subsequently heated, so that dopant,(e.g., phosphorous), from the doped oxide layer 8 penetrates into theneighboring areas of the p-conductive region 3 in order to form ann-conductive zone 7 thereat. This doped oxide layer 8 exhibits a layerthickness of about 0.1 through 0.5 μm, so that a remaining width b ofapproximately 1 μm also remains for the cavity 6.

Regardless of whether the method according to FIG. 1 (“trench etchingand epi-deposition”) or the method according to FIG. 2 (“trench etching,deposition of doped oxide and drive-out”) is implemented, it is criticalthat the cavity 6 remains with a width b of approximately 1 μm over adepth T of about 40 μm (adequate for 600 V).

Using the semiconductor arrangement according to FIG. 1 or FIG. 2, thesteps shown in FIGS. 3 through 5 are performed. After deposition of athin passivation layer 9 of, for example, silicon dioxide having a layerthickness of approximately 50 nm, a doped glass 10 such as, for exampleborophosphorous silicate glass, is applied onto the opening of thecavity 6 and is subsequently caused to flow in a vacuum, so that thestructure shown in FIG. 4 arises. The doped glass 10 is then etchedback, which can occur with wet-chemical etching in diluted hydrofluoricacid, in order to thus obtain a planar structure corresponding to FIG.5.

The cavity 6 with a width b of approximately 1 μm under vacuum remainsunder the doped glass.

FIG. 6 shows how a standard DMOS transistor having a source electrode S,a drain electrode D, a gate electrode G, a source contact 11 ofaluminum, gate contacts 12 of polycrystalline silicon and n⁺-conductivesource zones 14 can be constructed in p-wells 13 between the individualcavities 6 or, respectively, trenches 4. The gate contacts 12 arethereby embedded into an insulating layer 15 of, for example, silicondioxide.

FIG. 7 illustrates an exemplary embodiment in which the structure withthe DMOS transistor is produced first, and then the etching of thetrench 4 and the production of the cavity follow.

The invention thus enables a semiconductor component that can bemanufactured in a simple way, since the zones with alternatingconductivity type in alternation can be generated without further effortwith the assistance of the trenches 4, and the remaining cavities 6 canbe closed without further ado. The area requirement of the inventivesemiconductor component is also extremely slight since the zones thateffect the clearing of the charge carriers proceed vertically relativeto the principal faces, so that a high integration density can beachieved.

The above-described method and communication system are illustrative ofthe principles of the present invention. Numerous modifications andadaptions thereof will be readily apparent to those skilled in this artwithout departing from the spirit and scope of the present.

The inventive semiconductor component can advantageously be atransistor, particularly a vertical resurf transistor, or a diode,particularly a Schottky diode, or a capacitor as well.

What is claimed is:
 1. A semiconductor component comprising: asemiconductor body with two principal faces; at least two electrodeswherein at least one of said electrodes is provided on one of saidprincipal faces; and zones of a conductivity type opposite one anotherthat are arranged in alternation in said semiconductor body and extendperpendicularly to said two principal faces, an application of a voltageto said two electrodes mutually clearing said zones of charge carriersso that an essentially constant field strength is built up in saidsemiconductor body between said two electrodes said zones containing acavity that is closed by a glass layer or by a sputtered layer.
 2. Thesemiconductor component according to claim 1, wherein said cavity has atrench structure with a width of approximately 1 μm and a depth ofapproximately 40 μm.
 3. The semiconductor component according to claim2, wherein said cavity is closed at an end lying opposite an end at oneof said principal faces.
 4. The semiconductor component according toclaim 2, wherein said cavity is closed by said glass layer, and saidglass layer comprises doped borophosphorous silicate.
 5. Thesemiconductor component according to claim 1 wherein inside walls ofsaid cavity comprise a passivation layer.
 6. The semiconductor componentaccording to claim 5, wherein said passivation layer is a silicondioxide layer having a layer thickness of approximately 50 nm.